Image reading device and gain setting method in image reading device

ABSTRACT

An image reading device includes a CCD which photoelectrically converts optical information and outputs an image signal in an analog form, a PGA which receives an output from the CCD, amplifies the output with a programmable gain, and outputs the output, an ADC which receives an output from the PGA, A/D-converts the output, and outputs an image signal in a digital form, and a CPU which calculates a gain which makes an output from the ADC match a reference value by using an output from the ADC and the reference value, thereby setting a gain for the PGA. This arrangement makes it possible to set a gain in a short period of time and shorten the first copy time in an image forming apparatus or MFP system using the image reading device of this invention.

BACKGROUND OF THE INVENTION

[0001] In an image reading device such as a scanner used in an imageforming apparatus or MFP (Multi Functional Printing) system, a signaloutput from a CCD (Charge-Coupled Device) upon photoelectric conversionmust be amplified by using an amplifier before image processing. This isbecause outputs from the CCD contain variations in the light amount ofthe lamp, changes in light amount due to secular changes in the lamp,variations in mirror reflectivity, variations in CCD sensitivity, andthe like, and hence need to be set at a predetermined level before imageprocessing.

[0002] Conventionally, a gain is set in such a preamplifier in thefollowing manner.

[0003] First of all, the gain is set in advance to the minimummagnification in the early stage. The exposure lamp is then turned on toread light reflected by a white reference plate by using the CCD. Theanalog value of an output signal from the CCD is converted into adigital value and compared with a target value.

[0004] If they do not coincide with each other, the set gain value ofthe preamplifier is increased from the minimum magnification by apredetermined value. As described above, light reflected by the whitereference plate is read again by the CCD. The analog value of an outputsignal from the CCD is converted into digital value and compared withthe target value.

[0005] If they do not coincide with each other, the set magnification isincreased by a predetermined value. When a read output value reaches thetarget value or more after repetition of such operation, the gainsetting operation is finished. The gain is set to the resultant value.

[0006] Such a conventional gain setting method takes much time to obtaina gain with which an output signal having a target value can be obtainedfrom the CCD. This prolongs the time between turning on the power of theimage reading device and starting read operation. As a consequence, inan image forming apparatus or MFP system, the first copy time slowsdown, resulting in low customer satisfaction level.

[0007] The present invention has been made in consideration of the abovesituation, and has as its object to provide an image reading device anda gain setting method in the image reading device, which can shorten thetime taken for the image reading device to start read operation.

SUMMARY OF THE INVENTION

[0008] An image reading device of the present invention comprises a CCDwhich photoelectrically converts optical information and outputs animage signal in an analog form, a PGA which receives an output from theCCD, amplifies the output with a programmable gain, and outputs theoutput, an ADC which receives an output from the PGA, A/D-converts theoutput, and outputs an image signal in a digital form, and a CPU whichcalculates a gain which makes an output from the ADC match a referencevalue by using an output from the ADC and the reference value, andsetting a gain for the PGA.

[0009] The PGA may comprise an input terminal to which an output fromthe CCD is supplied, a first switch and first resistor connected inseries with each other between the input terminal and a node, a secondswitch and second resistor which are connected in series with each otherand connected in parallel with the first switch and first resistorbetween the input terminal and the node, . . . , and an nth switch andnth resistor which are connected in series with each other and connectedin parallel with the first switch and first resistor, the second switchand second resistor, . . . , and the (n−1) th switch and (n−1) thresistor between the input terminal and the node, an operationalamplifier whose inverting input terminal is connected to the node,non-inverting input terminal is grounded, and output terminal isconnected to an input terminal of the ADC, and an (n+1) th resistorconnected in series between the output terminal of the operationalamplifier and the node, and the CPU may set a gain by ON/OFF-controllingthe first switch, the second switch, . . . , and the nth switch.

[0010] This device can further comprise a document table, an exposurelamp which exposes a document placed on the document table, and a mirrorwhich reflects light reflected by the document exposed by the exposurelamp and supplies the light as the optical information to the CCD.

[0011] The CPU may use the reference value A and an output value B fromthe ADC when a gain of the PGA is an initial value to set a computationvalue C of A/B as a gain for the PGA.

[0012] The CPU may set a gain for the PGA by repeating processing ofcomparing the reference value R with an output value B1 from the ADCwhen a gain of the PGA is set to an initial value G1, setting the gainof the PGA to G1 if B1≧R, comparing the reference value R with an outputvalue B2 from the ADC obtained when the gain of the PGA is set to avalue G2 obtained by adding a predetermined value i to G1 if not B1≧R,setting the gain of the PGA to G1 if B2≧R, . . . , setting the gain ofthe PGA to Gn−1 if Bn−1 (n is an integer not less than 2)≧R, comparingthe reference value R with an output value Bn from the ADC obtained whenthe gain of the PGA is set to a value Gn obtained by adding thepredetermined value i to Gn−1 if no Bn−1≧R, and setting the gain of thePGA to Gn if Bn≧R, . . . .

[0013] A gain setting method in an image reading device according to thepresent invention comprises the step of photoelectrically convertingoptical information and outputting an image signal in an analog form byusing a CCD, the step of amplifying the image signal by using a PGAwhich can program a gain, the step of A/D-converting the amplified imagesignal by using an ADC and outputting an image signal in a digital form,and the step of using a CPU to calculate a gain which makes an outputfrom the ADC match a reference value by using an output from the ADC andthe reference value and to set a gain for the PGA.

[0014] In the step of setting the gain for the PGA, the reference valueA and an output value B from the ADC obtained when a gain of the PGA isan initial value may be used to set a computation value C of A/B as again for the PGA.

[0015] In the step of setting the gain for the PGA, a gain for the PGAmay be set by repeating processing of comparing the reference value Rwith an output value B1 from the ADC when a gain of the PGA is set to aninitial value G1, setting the gain of the PGA to G1 if B1≧R, comparingthe reference value R with an output value B2 from the ADC obtained whenthe gain of the PGA is set to a value G2 obtained by adding apredetermined value i to G1 if not B1≧R, setting the gain of the PGA toG1 if B2≧R, . . . , setting the gain of the PGA to Gn−1 if Bn−1≧R,comparing the reference value R with an output value Bn from the ADCobtained when the gain of the PGA is set to a value Gn obtained byadding the predetermined value i to Gn−1 if no Bn−1≧R, and setting thegain of the PGA to Gn if Bn≧R, . . . .

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a block diagram showing an outer appearance of an imagereading device according to an embodiment of the present invention;

[0017]FIG. 2 is a block diagram showing the circuit arrangement of theimage reading device;

[0018]FIG. 3 is a block diagram showing the arrangement of PGA(Programmable Gain Amplifier) in the image reading device;

[0019]FIG. 4 is a graph showing the relationship between the inputvoltage and output voltage for the PGA and the output value from an ADC(Analog Digital Converter) to which the output voltage from the PGA isapplied;

[0020]FIG. 5 is a flow chart showing a procedure for controlling thegain of the PGA in a conventional image reading device;

[0021]FIG. 6 is a flow chart showing a procedure for controlling thegain of the PGA in the image reading device according to the embodimentof the present invention;

[0022]FIG. 7 is a flow chart showing a procedure for controlling thegain of a PGA in an image reading device according to another embodimentof the present invention; and

[0023]FIG. 8 is a flow chart showing a generalized procedure as anexample of the procedure shown in FIG. 7.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] An embodiment of the present invention will be described belowwith reference to the accompanying drawings.

[0025]FIG. 1 shows the schematic arrangement of a scanner 1 as an imagereading device according to this embodiment.

[0026] The scanner 1 includes a document table 2, a first carriage 4having an exposure lamp 5 and a first mirror 6, a second carriage 7having a second mirror 8 and a third mirror 9, a lens 10, a CCD board 11on which a CCD 12 is mounted, a scanner control board 13 on which ascanner control circuit is formed, and a motor (not shown).

[0027] A document 3 is placed on the document table 2. The exposure lamp5 of the first carriage 4 exposes the document 3, and reflected light isreflected by the first mirror 6. The light reflected by the first mirror6 is reflected by the second mirror 8 and third mirror 9 of the secondcarriage 7. The CCD 12 receives the light reflected by the third mirror9 through the lens 10. The CCD 12 reads one line on the document 3 inthe main scanning direction.

[0028] When the first and second carriages 4 and 5 which are driven by amotor move in the sub-scanning direction, the whole document 3 can beread. The scanner control circuit formed on the scanner control board 13controls the operations of the motor, first carriage 4, second carriage7, and CCD 12.

[0029] In this manner, the light and shade of light reflected by thesurface of the document 3 are photoelectrically converted by the CCD 12to generate an analog signal. This signal is then binarized by abinarization circuit formed on the CCD board 11 or scanner control board13 and converted into a digital signal, as described later.

[0030]FIG. 2 shows a circuit arrangement for performing signalprocessing after photoelectric conversion in the scanner 1.

[0031] The analog signal output from a CCD 21 which represents the grayscale of an image is amplified to an amplitude necessary for A/Dconversion by a PGA (Programmable Gain Amplifier) 22.

[0032] The analog signal amplified by the PGA 22 is A/D-converted by anADC (Analog Digital Converter) and output as a binarized image signal.

[0033] This image signal is output from the scanner 1 after undergoing,for example, shading by the CCD 21, correction of variations unique tothe CCD 21, RGB correction, inter-line correction, lens aberrationcorrection, and the like. This signal is output to an external devicesuch as a printer 27. The output signal from an image correction circuit24 is stored in a memory 25 and supplied to a CPU (Central ProcessingUnit) 26 to be used to set a gain in the PGA 22.

[0034]FIG. 3 shows the arrangement of the PGA 22. The principle of gaincontrol will be described.

[0035] An input terminal IN1 of the PGA 22 is connected to the outputterminal of the CCD 21, and output terminal OUT1 is connected to theinput terminal of an ADC 23. Pairs of switch SW1 and resistor R1, switchSW2 and resistor R2, switch SW3 and resistor R3, . . . , and switch SWn(n is an integer equal to or more than 1) and resistor Rn which arerespectively connected in series are connected in parallel between theinput terminal IN1 and a node N1. The inverting input terminal of anoperational amplifier 33 is connected to the node N1, and itsnon-inverting input terminal is grounded. The output terminal ofoperational amplifier 33 is connected to the node N1 through a resistorRf and connected to an output terminal OUT1.

[0036] The operational amplifier 33 amplifies the value of the signaloutput from the CCD 21 in accordance with the input range of the ADC 23.The gain of the operational amplifier 33 must be set to make an inputvalue to the ADC 23 constant.

[0037] When all the switches SW1 to SWn are off, the gain of theoperational amplifier 33 is determined by the ratio of the resistor Rfto a resistor Rb. In normal times, Rf:Rb=1:1, and hence gain=1.

[0038] When the switch SW1 is turned on, the gain of the operationalamplifier 33 is determined by the ratio of the resistor Rf to theparallel-connected resistors Rb and R1. In this case, for example,R1//Rb is set to 1/2Rb, and hence gain=2.

[0039] When only the switch SW2 is turned on, the gain of theoperational amplifier 33 is determined by the ratio of the resistor Rfto the parallel-connected resistors Rb and R2. In this case, forexample, R2//Rb is set to 1/3Rb, and hence gain=3.

[0040] Likewise, when only the switch SW3 is turned on, gain=4 . . . ,and when only the switch SWn is turned on, gain=n+1.

[0041] In this case, the switches SW1, SW2, . . . , and SWn areON/OFF-controlled by the CPU 26 mounted on the scanner control board 13.

[0042] The principle of controlling the gain of the PGA in theconventional image reading device will be described below with referenceto FIG. 4. In the graph of FIG. 4, a PGA input voltage is plotted on theright side of the abscissa; PGA output voltage=ADC input voltage, on theordinate; and an output bit from the ADC, on the left side of theabscissa.

[0043] In the early stage, for example, the gain of the PGA is set to 1.Assume that the input voltage to the PGA is 0.2 V, and 255 bits arerequired as an output value from the ADC.

[0044] In the early stage, since gain=1, the output voltage from thePGA, i.e., the input voltage to the ADC, is 0.2 V, as indicated by astraight line L1 in FIG. 4. As a consequence, the ADC output becomes 25bits.

[0045] The 25 bits are compared with 255 bits which are a desired numberof bits. Since the above number of bits has not reached the desirednumber of bits, the gain is increased by one step, e.g., set to 2. Whengain=2, as indicated by a straight line L2 in FIG. 4, PGA outputvoltage=ADC input voltage becomes 0.4 V. As a result, the ADC outputbecomes 51 bits.

[0046] The 51 bits are compared with 255 bits which are the desirednumber of bits. Since the above number of bits has not reached thedesired number of bits, the gain is further increased by one step, e.g.,set to 3. When gain=3, as indicated by a straight line L3 in FIG. 4, PGAoutput voltage=ADC input voltage becomes 0.6 V. As a result, the ADCoutput becomes 76 bits.

[0047] This procedure is repeated to increase the gain one by one untilthe ADC output reaches 255. Straight lines L4, L5, L6, . . . , and L10respectively represent the relationships between the ADC input voltagesand the ADC output voltages when the gain is 4, 5, 6, . . . , and 10.When the gain reaches 10, the ADC output value reaches the desiredvalue, i.e., 255 bits.

[0048] When the ADC output reaches the desired output value, i.e., 255bits, the gain setting operation is completed.

[0049]FIG. 5 shows a procedure for PGA gain control in the conventionalimage reading device.

[0050] In step S10, a target value X (in this case, X=255) of an outputfrom the ADC is input to A.

[0051] In step S12, an initial value (in this case, 1) is input to again G.

[0052] In step S14, an output value from the ADC with the gain being setto the initial value is input to B.

[0053] In step S16, the output value B from the ADC is compared with thetarget value A to check whether B is equal to or more than A.

[0054] If B is less than A, a predetermined value (in this case, 1) isadded to the gain G in step S18. The flow then returns to step S14. WhenB reaches A or more, the gain setting processing is terminated.

[0055] As described, conventionally, many steps must be repeated, andhence it takes much time to set a gain.

[0056] In contrast, in this embodiment, gain setting processing isperformed by the procedure shown in the flow chart of Fig. 6.

[0057] In step S30, a target value X (in this case, X=255) of an outputfrom the ADC is input to A.

[0058] In step S32, an initial value (in this case, 1) is input to thegain G.

[0059] In step S34, an output value (in this case, 25 bits) from the ADC23 with gain G=initial value is input to B.

[0060] In step S36, the values of A and B are input to C=A/B tocalculate this equation, thereby obtaining the value of C (in this case,255/25=10).

[0061] In step S38, the obtained value of C is set to the gain G. Withthis operation, the gain setting processing is terminated.

[0062] As described above, according to this embodiment, a computationis performed by using an output voltage from the PGA 22 (an output valuefrom the ADC 23) and a target value in the early stage in which the gainis set to an initial value to determine a set gain value by onearithmetic process. This makes it possible to shorten the time requiredto set a gain. As a consequence, the first copy time can be shortened inan image forming apparatus or MFP system using the image reading deviceaccording to this embodiment, and hence the customer satisfaction can beincreased.

[0063] The above embodiment is an example and does not limit the presentinvention. This embodiment can be variously modified within thetechnical range of the present invention. In the arrangement shown in,for example, FIG. 1, the CPU 26 receives an output from the imagecorrection circuit 24 and compares it with a reference value to controlthe gain of the PGA 22. However, the CPU 26 may receive an output fromthe ADC 23 and compare it with a reference value to control the gain ofthe PGA 22.

[0064] In addition, the circuit arrangement of the PGA is not limited tothe one shown in FIG. 3, and any circuit arrangement can be used as longas gains can be set at predetermined intervals.

[0065] In the above embodiment, a set gain value is determined by onearithmetic process. In another embodiment to be described below,however, a set gain value is determined by a plurality of arithmeticprocesses. FIG. 7 shows a procedure for arithmetic processes in thiscase.

[0066] Assume that the following initial condition is set:

[0067] (1) CCD output voltage=0.7 (V)

[0068] (2) necessary input voltage to ADC≦2.0 (V)

[0069] (3) input voltage range for ADC=5.0 (V)

[0070] (4) output voltage range for ADC=255 (bits)

[0071] (5) peak detection threshold of ADC=2 (V)

[0072] (6) output at peak detection threshold of ADC=2 (V)/5 (V)=102(bits)

[0073] Under the above condition, the gain of the PGA is increased to 1dB, 2 dB, 3 dB, . . . . An output value (bits) from the ADC at each gainis compared with the necessary output value (≧102 (bits)). A set gainvalue is set to the gain set when this output value reaches thenecessary output value or more, and the processing is terminated.

[0074] In step S100 in FIG. 7, the target value X (=102) of an outputfrom the ADC is input to A.

[0075] In step S102, an initial value (=1) is input to a gain G.

[0076] In step S104, an output value (=36 bits) from the ADC with gainG=initial value (=1) is input to B.

[0077] In step S106, it is checked whether B≧A. If this condition issatisfied, the processing is terminated. Otherwise, the flow advances tostep S110.

[0078] In step S110, gain G=2 is set.

[0079] In step S112, an output value (=71 bits) from the ADC with gainG=2 is input to B.

[0080] In step S114, it is checked whether B≧A. If this condition issatisfied, the processing is terminated. Otherwise, the flow advances tostep S120.

[0081] In step S120, gain G=3 is set.

[0082] In step S122, an output value (=107 bits) from the ADC with gainG=3 is input to B.

[0083] In step S124, it is checked whether B≧A. In this case, since thiscondition is satisfied, the gain setting processing is terminated.

[0084] In this manner, the gain of the PGA is increased by adding apredetermined value to the initial value, and the gain obtained when anoutput value from the ADC reaches a desired value or more is set as aset gain value. This makes it possible to finish setting processing in ashorter period of time than in the prior art.

[0085] The flow chart of FIG. 8 shows a more generalized procedure.

[0086] In step S200, a target value X of an output from the ADC is inputto A.

[0087] In step S202, an initial value G0 is input to a gain G1.

[0088] In step S204, an output value from the ADC with gain G1=G0 isinput to B1.

[0089] In step S206, it is checked whether B1≧A. If this condition issatisfied, the processing is terminated. Otherwise, the flow advances tostep S210.

[0090] In step S210, the value obtained by adding a predetermined valuei to the gain G1 is set as a gain G2.

[0091] In step S212, an output value from the ADC with gain G2=G1+i isinput to B2.

[0092] In step S214, it is checked whether B2≧A. If this condition issatisfied, the processing is terminated. Otherwise, the flow advances tostep S220.

[0093] In step S220, the value obtained by adding the predeterminedvalue i to the gain G2 is set as a gain G3.

[0094] In step S222, an output value from the ADC with gain G3=G2+i isinput to B3.

[0095] In step S224, it is checked whether B3≧A. If this condition issatisfied, the processing is terminated. Otherwise, the flow advances tostep S230.

[0096] In step S230, the value obtained by adding the predeterminedvalue i to a gain Gn−1 (n is an integer equal to or more than 2) is setas a gain Gn.

[0097] In step S232, an output value from the ADC with gain Gn=Gn−1+i isinput to Bn.

[0098] In step S234, it is checked whether Bn≧A. If this condition issatisfied, the processing is terminated. Otherwise, the above steps arerepeated until Bn≧A is satisfied.

[0099] As described with reference to FIG. 7, the gain of the PGA isincreased by adding a predetermined value to the initial value inaccordance with the flow chart of FIG. 8, and the resultant output valuefrom the ADC is compared with a desired value. The gain obtained whenthe output value reaches the desired value is set as a set gain value,thereby completing the processing within a shorter period of time thanin the prior art.

What is claimed is:
 1. An image reading device comprising: a CCD whichphotoelectrically converts optical information and outputs an imagesignal in an analog form; a PGA which receives an output from said CCD,amplifies the output with a programmable gain, and outputs the output;an ADC which receives an output from said PGA, A/D-converts the output,and outputs an image signal in a digital form; and a CPU whichcalculates a gain which makes an output from said ADC match a referencevalue by using an output from said ADC and the reference value, andsetting a gain for said PGA.
 2. A device according to claim 1, whereinsaid PGA comprises: an input terminal to which an output from said CCDis supplied; a first switch and first resistor connected in series witheach other between the input terminal and a node; a second switch andsecond resistor which are connected in series with each other andconnected in parallel with the first switch and first resistor betweenthe input terminal and the node; an nth switch and nth resistor whichare connected in series with each other and connected in parallel withthe first switch and first resistor, the second switch and secondresistor, . . . , and the (n−1)th switch and (n−1)th resistor betweenthe input terminal and the node; an operational amplifier whoseinverting input terminal is connected to the node, non-inverting inputterminal is grounded, and output terminal is connected to an inputterminal of said ADC; and an (n+1)th resistor connected in seriesbetween the output terminal of the operational amplifier and the node,and said CPU sets a gain by ON/OFF-controlling the first switch, thesecond switch, . . . , and the nth switch.
 3. A device according toclaim 1, further comprising: a document table; an exposure lamp whichexposes a document placed on said document table; and a mirror whichreflects light reflected by the document exposed by said exposure lampand supplies the light as the optical information to said CCD.
 4. Adevice according to claim 1, wherein said CPU uses the reference value Aand an output value B from said ADC when a gain of said PGA is aninitial value to set a computation value C of A/B as a gain for saidPGA.
 5. A device according to claim 1, wherein said CPU sets a gain forsaid PGA by repeating processing of comparing the reference value R withan output value B1 from said ADC when a gain of said PGA is set to aninitial value G1, setting the gain of said PGA to G1 if B1≧R, comparingthe reference value R with an output value B2 from said ADC obtainedwhen the gain of said PGA is set to a value G2 obtained by adding apredetermined value i to G1 if not B1≧R, setting the gain of said PGA toG1 if B2≧R, . . . , setting the gain of said PGA to Gn−1 (n is aninteger not less than 2) if Bn−1≧R, comparing the reference value R withan output value Bn from said ADC obtained when the gain of said PGA isset to a value Gn obtained by adding the predetermined value i to Gn−1if no Bn−1≧R, and setting the gain of said PGA to Gn if Bn≧R, . . . . 6.A gain setting method in an image reading device, comprising: the stepof photoelectrically converting optical information and outputting animage signal in an analog form by using a CCD; the step of amplifyingthe image signal by using a PGA which can program a gain; the step ofA/D-converting the amplified image signal by using an ADC and outputtingan image signal in a digital form; and the step of using a CPU tocalculate a gain which makes an output from the ADC match a referencevalue by using an output from the ADC and the reference value to and seta gain for the PGA.
 7. A method according to claim 6, wherein in thestep of setting the gain for the PGA, the reference value A and anoutput value B from the ADC obtained when a gain of the PGA is aninitial value are used to set a computation value C of A/B as a gain forthe PGA.
 8. A method according to claim 6, wherein in the step ofsetting the gain for the PGA, a gain for the PGA is set by repeatingprocessing of comparing the reference value R with an output value B1from the ADC when a gain of the PGA is set to an initial value G1,setting the gain of the PGA to G1 if B1≧R, comparing the reference valueR with an output value B2 from the ADC obtained when the gain of the PGAis set to a value G2 obtained by adding a predetermined value i to G1 ifnot B1≧R, setting the gain of the PGA to G1 if B2≧R, . . . , setting thegain of the PGA to Gn−1 if Bn−1≧R, comparing the reference value R withan output value Bn from the ADC obtained when the gain of the PGA is setto a value Gn obtained by adding the predetermined value i to Gn−1 if noBn−1≧R, and setting the gain of the PGA to Gn if Bn≧R, . . . .